Bridging Communications: Developing Hardware/Software Interfaces for Hardware Accelerators

As we approach the physical limits of hardware, as dictated by Moore's Law, the need for innovative solutions to sustain performance improvements becomes critical. To overcome these constraints, the use of specialized hardware accelerators has become increasingly important in modern computer architecture. In this context, integrating accelerators like the Real-Time Hardware Sorter (RTHS) presents significant challenges. The RTHS is designed to sort data inputs in parallel using a multidimensional algorithm, combining bitonic sorting networks with pipelined processing for rapid, efficient operations. However, integrating such accelerators presents challenges, including mismatches in interface standards, coherency protocols, and memory alignment requirements. Addressing these issues is essential to fully harnessing the potential of specialized accelerators and sustaining performance gains. To tackle these challenges, we utilized the Cohort platform to develop a seamless hardware/software interface for the RTHS. Initially, we tested the RTHS in isolation using a Cocotb testbench, establishing its signals and confirming its functionality. We later developed an interface, managed by a finite state machine, that ensures efficient communication between the RTHS and software. Currently, we are working on the integration process. This study provides a robust solution to integration challenges in heterogeneous computing systems.

Faculty Mentors: Jonathan Balkind, Tim Sherwood

Project Mentors: Brian Li, Nazereke Turtayeva